Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 105

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Interrupt Condition (Active RDY)
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Interrupt service routines on a Z80 CPU always end with a Return From
Interrupt (RETI or hex ED4D) instruction, which is now explained.
Figure 36.
Return From Interrupt
At the end of an interrupt service routine, the Z80 CPU executes a return-
from-interrupt (RETI or hex ED4D) instruction. This returns the CPU from
the interrupt service routine.
The DMA also simultaneously decodes the RETI instruction, which it
recognizes on the data bus as an instruction (occurring when the DMA’s
M1 input is Low). This causes at least one, and possibly two, events within
the DMA:
Reset and Disable Interrupts
Reset and disable DMA interrupts
–
–
Load new starting addresses and block length
–
–
Force the Ready condition
Read the status byte
–
–
*NOTE: This latch is only set when the Interrupt-On-Ready option is selected.
Enable DMA interrupts
Disable DMA interrupts
Continue prior address counting
Clear block length counter
Initiate a status-register read sequence
Clear status
Enable after RETI
Interrupt On Ready (IOR) Latch
+5V
D-FLIP-FLOP
CY
D
R
IOR
O
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
Disable DMA
7 U G T / C P W C N