Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 263

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6. Bisync Transmit Mode (Continued)
UM008101-0601
Function
Idle Mode
Data Transfer and
Status Monitoring
Termination
WR0
WR5
Typical Program Steps
Pointer 5
Request To Send, Transmit Enable, Bisync
CRC, transmit character length first Sync
Byte To SIO
Execute Halt Instruction or some other
program
When Interrupt (WAIT/READY) occurs: Interrupt Occurs (Wait/ready
• Include/Exclude data byte from CRC
Accumulation (in SIO)
• Transfer data byte from CPU (or
memory) to SIO
• Detect and set appropriate flags for
control characters (in CPU)
• Reset Tx Underrun/EOM Latch WR0 if
last character of message is detected
• Update pointers and parameters (CPU)
Return from Interrupt
If Error Condition Or Status Change
Occurs:
• Transfer RR0 to CPU
• Execute Error Routine
• Return From Interrupt
Redefine Interrupt Modes, Update Modem
Control outputs (for example, turn off
RTS)
Disable Transmit Mode
Comments
Status affects vector (Channel B
only). Transmit CRC Enable should
be set when first non-sync data is
sent to Z80 SIO. Need several sync
characters in the beginning of
message. Transmitter is fully
initialized.
Waiting for interrupt or WAIT/
READY output to transfer data.
Becomes Active) When first data
byte is being sent, Wait Mode allows
CPU block transfer from memory to
SIO; Ready Mode allows DMA
block transfer from memory to SIO.
The DMA chip can be programmed
to capture special control characters
(by examining only the bits that
specify ASCII or EBCDIC control
characters), and interrupt CPU.
Tx Underrun/EOM indicates either
Transmit Underrun (sync character
being sent) or end of message (CRC-
16 being sent).
Program should gracefully terminate
message
Z80 CPU Peripherals
Serial Input/Output
User Manual
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