Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 223
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
If a sensor puts a High level on lines A5, A3, or A0, an interrupt request is
generated. The mask word may select any combination of inputs or
outputs to cause an interrupt. For example, if the mask word above is:
then an interrupt request would also occur if bit A7 (Special Test) of the
output register was set.
Assume that the following port assignments are to be used:
All port numbers are in hexadecimal notation. This particular assignment of
port numbers is convenient because A0 of the address bus can be used as
the Port B/A Select and A1 of the address bus can be used as the Control/
Data Select. The Chip Enable is the decode of CPU address bits A7 through
A2 (
Note: When only a few peripheral devices are being used, a Chip Enable
decode may not be required because a higher order address bit may be
used directly.
D7
D7
0
1
111000
Selects A5, A3, and A0 to be Monitored
D6
D6
1
1
D5
0
D5
0
E0H = Port A Data
E1H = Port B Data
E2H = Port A Control
E3H = Port B Control
).
D4
1
D4
1
D3
D3
0
0
D2
D2
1
1
D1
D1
1
1
D0
D0
0
0
< % 2 7 2 G T K R J G T C N U
Parallel Input/Output
7 U G T / C P W C N
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