Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 12

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xii
UM008101-0601
Z80 CPU Peripherals
User Manual
Direct Memory Access (continued)
Parallel Input/Output
Figure 74. WAIT Line Sampling in Variable-Cycle Timing . . . . . . 167
Figure 75. Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 76. Write Register 0 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 77. Write Register 1 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 78. Write Register 2 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 79. Write Register 3 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 80. Write Register 4 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 81. Write Register 5 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 82. Write Register 6 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 83. Read Register 0 through 6 Bit Functions . . . . . . . . . . . . . 174
Figure 84. PIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 85. Port I/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 86. PIO Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 87. 44-Pin PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . 185
Figure 88. 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . 186
Figure 89. 40-Pin DIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 187
Figure 90. Mode 0 (Output) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 91. Mode 1 (Input) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 92. Port A, Mode 2 (Bidirectional) Timing . . . . . . . . . . . . . . 195
Figure 93. Control Mode (Mode 3) Timing . . . . . . . . . . . . . . . . . . . 196
Figure 94. Interrupt Acknowledge Timing . . . . . . . . . . . . . . . . . . . . 198
Figure 95. Return from Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . 198
Figure 96. Daisy-Chain Interrupt Servicing . . . . . . . . . . . . . . . . . . . 199
Figure 97. A Method of Extending the Interrupt Priority
Daisy-Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
List of Figures