Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 94

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11. Contents of Counters After DMA Stops Because of End-of-Block (Transfer
Operations)
Table 12. Contents of Counters After DMA Stops Due to Byte Match (Search or Transfer/
Search Operations)
UM008101-0601
Sequential
Transfer
Search Only or
Simultaneous
Transfer/Search
Class
Sequential
Transfer
Search Only or
Simultaneous
Transfer Search
* Address can increment (+) or decrement (-) from the programmed starting address (As), which is the first
address for transfer purposes.
** Occurs only in 2-cycle (variable timing) simultaneous transfers when the Ready line is still active at the end
of the N + 1 byte transfer.
*** Simultaneous transfers cannot have both ports variable. This class of operation is programmed as a DMA
search-only operation, with variable addresses ascribed to the programmed source port. What the DMA senses
is the source port may be either the real source or destination, as determined by external hardware. See “The
actual number of bytes transferred is one more than specified by the block length.
necessary only in the case of a fixed destination address.” on page 129.
Notes
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Class
:
Mode
Byte
Burst
Continuous
Byte
Burst
Burst
Continuous
Mode
Byte
Burst
Continuous
Byte
Burst
Burst
Continuous
Continuous
Match Occurs
On This Byte
M
M
M
M
M
M
M
Programmed
Block Length
N
N
N
N
N
N
N+1
N+1
Bytes Transferred At Stop
If Transferring
M
M
M+
M
M+1
M**
M+1
Bytes Transferred
At Stop
N+1
N+1
N+1
N+1
N+1
N+2**
N+1
N+2**
Byte Counter
N
N
N
N
N+1
N+1 **
N+1
N+1 **
Byte Counter
M-1
M-1
M-1
M
M+1
M-1**
M+1
Source Port
Address Counter*
As±(N+1)
As±(N+1)
As±(N+1)
As±(N+1)
As±(N+1)
As±(N+2)**
As±(N+1)
As±(N+2)**
Source Port
Address Counter*
As±(M)
As±(M)
As±(M)
As±(M)
As±(M+1)
As±(M**
As±(M+1)
Direct Memory Access
* These entries are
Destination Port
Address Counter*
As±(N)
As±(N)
As±(N)
***
***
***
***
***
Destination Port
Address Counter
As±(M-1)
As±(M-)
As±(M -)
***
***
***
***