Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 74

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Transfer Speed
The Z80 DMA has one of the fastest maximum transfer rates of any 8-bit
DMAC device. This rate is achieved in the simultaneous transfer class of
operation and, unlike the more common sequential transfer class, it requires
at least one external TTL package. But because some other 8-bit DMAs
require some external logic, this constitutes a legitimate speed comparison.
Table 8 describes the maximum rates that can be achieved in different
classes of DMA operation. Maximum CPU block-transfer rates are also
given for comparison. All DMA transfers assume the uninterrupted use of
Burst or Continuous mode, and they assume read and write cycles that last
two cycles (see “Variable Cycle” on page 60).
Transfer speed in Byte mode depends on how long the CPU keeps the bus
between each byte transfer of the DMA. Therefore, the speed is best
expressed from the CPU viewpoint.
Table 9 describes the reduction in Z80 throughput (per Kilobaud trans-
ferred) caused by byte-mode DMA transfers, and this rate is compared with
the reduction in throughput that would occur if the CPU did its own byte
transfers using an interrupt service routine of six instructions (a practical
lower limit). “Z80 DMA and Z80 SIO Example” on page 139 contains
more detail on this data. This data assumes sequential DMA transfers with
longer cycle timing than the minimum of two clock cycles per read or
write. Simultaneous transfers of two clock cycles would, therefore, result in
even lower impact on CPU throughput.
Table 8 describes that DMA transfer rates in Burst and Continuous modes
can be up to ten times faster than Z80 CPU rates. Table 9 describes that the
reduction of CPU throughput with Byte mode DMA transfers is about five
times less than the reduction that results when the CPU handles its own
byte-mode I/O in the normal interrupt mode.
Direct Memory Access