Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 103

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Disable Interrupts
Enable Interrupts
If the Interrupt on RDY (interrupt before requesting bus) option is selected,
the IP latch is set when the Ready line becomes active, causing INT to go
Low.
The IP latch is reset whenever the IUS latch is se. If the interrupt causing
condition is not removed before IUS reset, IP becomes set again after IUS
reset, causing another interrupt. The US latch can be reset by the Z80
CPU’s Return from Interrupt (RETI) instruction or by control bytes written
to the DMA.
Figure 34.
Reset and Disable Interrupts
Figure 35.
Reset and Disable Interrupts
–
–
Interrupt Acknowledge
*NOTE: Interrupt conditions can include end-of-block,
Reinitialize Status Byte
Interrupt Pending
Prevents interrupts from lower priority devices in an interrupt
daisy-chain
Prevents further bus requests by this DMA
Interrupt Condition
(M1 and IORQ)
(from IP Latch)
byte match, or active RDY line, depending on programming.
Interrupt Pending (IP) Latch
Interrupt Under Service (IUS) Latch
M1 Inactive
S
R
RETI
IEI
Q
S
R
R
S
<   % 2 7 2 G T K R J G T C N U
IP
IUS
Direct Memory Access
O
O
7 U G T / C P W C N
Interrupt Pending
(To IUS Latch Set)
Disable DMA