Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 158

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
The event sequences for SIO-DMA transfers are described in Table 17 and
Table 18.
Table 17. Receive Event Sequence
Table 18. Transmit Event Sequence
Event
SIO transmits last bit of character 5-6
SIO RDY becomes true
DMA asserts BUSREQ
Current CPU machine cycle ends 1
CPU asserts BUSACK
DMA memory read cycle begins
Event
SIO receives last bit of character 10-13
SIO RDY becomes active
DMA asserts BUSREQ
Current CPU machine cycle ends 1
CPU asserts BUSACK
DMA I/O read cycle begins
DMA memory write cycle begins 2
DMA terminates BUSREQ
DMA memory write cycle ends
CPU terminates BUSACK and
regains control of bus
Note: Latency (delay from reception of final data bit to reading of received data) is 22 to
29 clock periods. The system bus is occupied by the DMA for 13 clock periods per byte
transferred.
Inter-event delay
(clock periods)
2
1-5
4
3
Inter-event delay
(clock periods)
2
1-5
4
4
1
1
1
Direct Memory Access
latency
latency
latency
latency, bus occupancy
latency, bus occupancy
latency, bus occupancy
bus occupancy
bus occupancy
bus occupancy
bus occupancy
latency
latency
latency
latency, bus occupancy
latency, bus occupancy
latency, bus occupancy