Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 136

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Review of Programming Sequences
Table 11 and Table 12 illustrate how the pipelining of data affects the
number of bytes transferred or searched in the various classes, modes, and
circumstances of operation. In most cases, the number of bytes transferred
in a transfer operation that stops at end-of-block is one more than the
programmed block length.
When the pulse-generation feature is used, the contents of the pulse control
byte in WR4 are compared with the lower byte of the byte counter after
each byte is transferred.
Port A Address Counter (RR3, RR4)
This 16-bit counter is loaded from the Port A starting address register in
WR0 by the LOAD command. It increments, decrements, or remains fixed
according to the specifications in WR1. Table 11 and Table 12 show how
this counter reads under various transfer or search conditions.
Port B Address Counter (RR5, RR6)
This counter is identical to the Port A address counter just described. If
either Port A or Port B is a fixed-address destination port, it must be
programmed as described in “Fixed-Address Destination Ports” on
page 121 to function properly.
This section describes programming the DMA in both the general and in
application-specific cases. Also, see Table 16 on page 127 for a sample
DMA Program.
DMA Initialization
Program all registers to be used in the DMA at power-up. None of these
registers contain useful defaults. This procedure includes the enabling of
Direct Memory Access