Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 129

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
6. •
7. •
8. •
RETI instruction
Read Status Byte (BF)
This command causes the next CPU read of the DMA to access the status
byte, which is illustrated in “Read Registers” on page 114.
If other read registers are being read, the sequence of reading (as defined by
the read mask) must be completed before issuing this command.
Reinitialize Status Byte (8B)
This command reinitializes bits 4 and 5 of the status byte. After reinitial-
ization, the status byte looks like this:
Table 14. Reinitialize Status Byte
The DISABLE DMA or any other command must be used before the
REINITIALIZE STATUS BYTE command after having stopped on end-of-
block or byte match. Due to a potential hardware race condition internal to
Bit
0
1
2
3
4
5
6
7
Value
I/O
I/O
X
0/1
1
1
X
X
Meaning
DMA operation has/has not occurred
Ready line active/inactive
Undefined bit
Interrupt pending/not pending
Match not found
Not end-of-block
Undefined bit
Undefined bit
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N