Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 284

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

264
Table 9. SDLC Transmit Mode (Continued)
UM008101-0601
Function
Data Transfer and
Status
Monitoring
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Typical Program Steps
When Interrupt (Wait Ready)
occurs, the CPU performs the
following:
• Changes Transmit Word
Length (if necessary)
• Transfers Data Byte from
CPU (memory) to SIO
• Resets Tx Underrun/EOM
Latch WR0
If the last character of the I-
Field is sent, the SIO performs
the following:
• Sends CRC
• Sends Closing Flag
• Interrupts CPU with Buffer
Empty status
The CPU performs the
following:
• Issues Reset Tx Interrupt
Pending Command to the Z80
SIO
• Updates NS count
• Repeats the process for next
message, and more.
If the Vector Indicates an error,
the CPU performs the
following:
• Sends Abort
• Executes Error Routine
• Updates Parameters, Modes,
and more
Comments
Flags are transmitted by the SIO as soon as
Transmit Enable is set and CTS becomes active.
The CTS status change is the first interrupt that
occurs and is followed by transmit buffer empty
for subsequent transfers. Word length can be
changed on-the-fly for variable I-Field length.
The data byte can contain address, control, or I-
Field information, but not a flag. Reset Tx
Underrun/EOM Latch in the beginning of the
message to avoid a false end-of-frame detection
at the receiving end. This ensures that, when
underrun occurs, CRC is transmitted and
Underrun Interrupt (Tx Underrun/EOM Latch
active) occurs. Send Abort can be issued to the
SIO in response to any interrupting, continuing
to abort the transmission.
Serial Input/Output