Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 256

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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used. If parity is enabled, the parity bit is not stripped from the assembled
character for character lengths other than eight bits. For lengths other than
eight bits, the receiver assembles a character length of the required
number of data bits, plus a parity bit and Is for any unused bits. For
example, the receiver assembles a 5-bit character with the following
format: 11 P D4 D3 D2 D1 D0.
Because the receiver is buffered by three 8-bit registers in addition to the
receive shift register, the CPU has enough time to service an interrupt and
to accept the data character assembled by the Z80 SIO. The receiver also
has three buffers that store error flags for each data character in the receive
buffer. These error flags are loaded at the same time as the data characters.
After a character is received, it is checked for the following error conditions:
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•
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When parity is enabled, the Parity Error bit (RR1, D4) is set whenever
the parity bit of the character does not match with the programmed
parity. Once this bit is set, it remains set until the Error Reset Command
(WR0) is given.
The Framing Error bit (RR1, D6) is set if the character is assembled
without any stop bits (that is, a Low level detected for a stop bit).
Unlike the Parity Error bit, this bit is set (and not latched) only for the
character on which it occurred. Detection of framing error adds an
additional one-half of a bit time to the character time so the framing
error is not interpreted as a new start bit.
If the CPU fails to read a data character while more than three
characters have been received, the Receive Overrun bit RR1 D5) is set.
When this occurs, the fourth character assembled replaces the third
character in the receive buffers. With this arrangement, only the
character that has been written over is flagged with the Receive Overrun
Error bit. Like Parity Error, this bit can only be reset by the Error Reset
command from the CPU. Both the Framing Error and Receive Overrun
Error cause an interrupt with the interrupt vector indicating a Special
Receive condition (if Status Affects Vector is selected).
Serial Input/Output