Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 255
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
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Table 4. Asynchronous Mode (Continued)
UM008101-0601
Function
Termination
Asynchronous Receive
An Asynchronous Receive operation begins when the Receive Enable bit is
set. If the Auto Enables option is selected, DCD must be Low. A Low
(spacing) condition on the Receive Data input (RxD) indicates a start bit. If
this Low persists for at least one-half of a bit time, the start bit is assumed to
be valid and the data input is then sampled at mid-bit time until the entire
character is assembled. This method of detecting a start bit improves error
rejection when noise spikes exist on an otherwise marking line.
If the x1 clock mode is selected, bit synchronization must be accom-
plished externally. Receive data is sampled on the rising edge of RxC.
The receiver inserts 1s when a character length of other than eight bits is
If External Status changes:
• Transfer RRD to CPU
• Perform Error routines (include Break
detection)
• Return from Interrupt
If special receive condition occurs:
• Transfer RR1 to CPU
• D6 Special Error (such as framing error)
routine
• Return from Interrupt
Redefine Receive/Transmit Interrupt modes
Disable Transmit/Receive modes
Update modem control outputs (such as RTS
off)
Typical Program Steps
Comments
If used with processors other
than the Z80, the modified
interrupt vector (RR2) should
be returned to the CPU in the
interrupt acknowledge
sequence.
When Transmit or Receive
Data transfer is complete.
In Transmit, the all sent status
bit indicates transmission is
complete.
Z80 CPU Peripherals
Serial Input/Output
User Manual
235
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