Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 326

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

306
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Interrupt Acknowledge Cycle
IORQ
Figure 129. Write Cycle Timing
After receiving an Interrupt Request signal, INT pulled Low, the Z80 CPU
sends an Interrupt Acknowledge signal, M1 and IORQ, both Low. The
daisy-chained interrupt circuits determine the highest priority interrupt
requestor. The IEI of the highest priority peripheral is terminated High.
Peripherals that have no interrupt pending or under service are terminated
IEO = IEI. Any peripheral that does have an interrupt pending or under
service, forces its IEO Low.
To insure stable conditions in the daisy-chain, all interrupt status signals are
prevented from changing while MI is Low. When IORQ is Low, the highest
priority interrupt requestor, which is the one with IEI High, places its
interrupt vector on the data bus and sets its internal interrupt-underservice
latch. See Figure 130.
Data
RD
CE
M1
Φ
T
1
T
2
Channel Address
T
W
In
T
3
Serial Input/Output
T
1