Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 138

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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Table 15. Control Byte Order (Continued)
Port Designation
Either Port A or Port B can be selected as the source or destination, (illus-
trated in Figure 19) because both ports feature the same degree of program-
mability. When the destination port is also a fixed-address port, see the
section “Fixed-Address Destination Ports.” Port characteristics are spec-
ified in the following control byte groups:
In a transfer, if the direction of transfer (bit 2 of WR0) changes, the WR0
control byte must be preceded by a different control byte, thereby insuring
that the DMA is disabled.
Initialization/Reinitialization Sequence
REINITIALIZE STATUS BYTE
Command
READ MASK FOLLOWS Command
Read Mask Control Byte
INITIATE READ SEQUENCE
Command
FORCE READY Command
ENABLE INTERRUPTS Command
ENABLE DMA Command
Total
Port A
WR0
WR1
WR6
Port B
WR0
WR2
WR4
WR6
Maximum Number of Z80 CPU
Bytes
1
1
1
1
1
1
1
35
Direct Memory Access