Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 181

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
BUSREQ
search (Figure 69). The action on BUSREQ is thus somewhat delayed from
action on the RDY line. The DMA always completes the current byte oper-
ation in an orderly fashion before releasing the bus.
Figure 69.
By contrast, BUSREQ is not released in Continuous mode when RDY goes
inactive. Instead, the DMA idles after completing the current byte opera-
tion, awaiting an active RDY again.
Figure 70, Figure 71, and Figure 72 review the relationship between the
Ready line going inactive and the state of the other lines for each mode of
operation, assuming a search-only of memory using standard Z80 timing.
The timing for Ready coming active is discussed under Bus Request. RDY
is sampled on the rising edge of CLK in the last clock cycle of each read or
write cycle. It is a level-sample, not an edge-sample. RDY can go inactive
prior to the completion of the last byte operation without disturbing that
operation. At the end of that operation, the BUSREQ and BAI lines go
High in Byte or Burst mode according to Figure 68 and Figure 71. The bus
control lines MREQ, IORQ, RD, and WR, also remain High in Byte and
Burst mode during an inactive RDY, with both the address and data buses
tristated.
The Continuous mode (Figure 72) is different because the address bus
holds the pre incremented address for the next byte throughout the time
that RDY is inactive. This address is immediately available when RDY
comes active again.
RDY
CLK
Active
Inactive
Bus Release on Not Ready (Burst Mode)
Current Byte
Operation
DMA
Inactive
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N