Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 15

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

List of Tables
List of Tables
Counter/Timer Channels
Direct Memory Access
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Channel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Channel Select Truth Table . . . . . . . . . . . . . . . . . . . . . . . . .13
Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .19
Time Constant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . .23
Maximum Transfer and Search Speeds (Burst and Continuous
Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Reduction in Z80 CPU Throughput per Kbaud
(Byte Mode Transfers) . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Events and Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Contents of Counters After DMA Stops Because of End-of-
Block (Transfer Operations) . . . . . . . . . . . . . . . . . . . . . . . .76
Contents of Counters After DMA Stops Due to Byte Match
(Search or Transfer/Search Operations) . . . . . . . . . . . . . . .76
DMA Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Reinitialize Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Control Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Sample DMA Program . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Receive Event Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .139
Transmit Event Sequence . . . . . . . . . . . . . . . . . . . . . . . . .139
Z80 CPU Peripherals
User Manual
UM008101-0601
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