Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 77

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Interrupts
The match byte written into the DMA is masked with another byte so that
only certain bits within the match byte can be compared with the corre-
sponding bits in the data bytes being searched.
The DMA can be programmed to interrupt the CPU on three conditions:
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•
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The first condition (I/O-port Ready line becoming active) causes an
interrupt before the DMA requests the bus. The other two conditions
cause the DMA to interrupt the CPU after the DMA stops (releases the
bus). Stopping the DMA on byte match or end-of-block is separately
programmed.
Any of these conditions (Ready line becoming active, byte match, or end-
of-block) causes a readable status bit to be set. In addition, when an
interrupt on any of these conditions is programmed, an interrupt-pending
status bit is also set, and each type of interrupt can optionally alter the
DMAs interrupt vector.
The DMA shares the Z80 Family’s versatile interrupt scheme, which
provides fast interrupt service in real-time applications. In a Z80 CPU
environment where the CPU is using its Mode 2 interrupts, the DMA
passes its internally modifiable 8-bit interrupt vector to the CPU, which
attaches an additional eight bits to form the memory address of the
interrupt routine table. This table contains the address of the beginning of
the interrupt routine. In this process, CPU control is transferred to the
interrupt routine, so that the next instruction executed after an interrupt
acknowledge is the first instruction of the interrupt routine.
Interrupt on Ready
Interrupt on Byte Match
Interrupt on End-of-Block
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
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