Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 200
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
Z0847006PSG
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PIN DESCRIPTION
UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Figure 3 illustrates a diagram of the Z80 PIO pin configuration. This
section describes the function of each pin.
D7-D0
Z80 CPU Data Bus (bidirectional, tristate). This bus is used to transfer all
data and commands between the Z80 CPU and the Z80 PIO. D0 is the
least-significant bit of the bus.
B/A Sel
Port B or A Select (input, active High). This pin defines which port is
accessed during a data transfer between the Z80 CPU and the Z80 PIO. A
Low level on this pin selects Port A while a High level selects Port B.
Often, Address bit A0 from the CPU is used for this selection function.
C/D Sel
Control or Data Select (input, active High). This pin defines the type of
data transfer to be performed between the CPU and the PIO. A High level
on this pin during a CPU write to the PIO causes the Z80 data bus to be
interpreted as a command for the port selected by the B/A Select line. A
Low level on this pin means that the Z80 data bus is being used to transfer
data between the CPU and the PIO. Often, Address bit Al from the CPU is
used for this function.
CE
Chip Enable (input, active Low). A Low level on this pin enables the PIO to
accept command or data inputs from the CPU during a write cycle or to
transmit data to the CPU during a read cycle. This signal is generally a decode
of four I/O port numbers that encompass Ports A and B, data, and control.
Parallel Input/Output
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