Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 268

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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7 U G T / C P W C N
Transmit Transparent Mode
Transparent mode (Bisync protocol) operation is made possible by the
ability to change Transmit CRC Enable on the fly and by the additional
capability of inserting 16-bit sync characters. Exclusion of IDLE characters
from CRC calculation can be achieved by disabling CRC calculation
immediately preceding the IDLE character transfer to the Z80 SIO.
In the case of a Transmit Underrun condition in the Transparent mode, a
pair of DLE-SYN characters are sent. The Z80 SIO can be programmed to
send the DLE-SYN sequence by loading a IDLE character to WR6 and a
sync character to WR7.
Transmit Termination
The Z80 SIO is equipped with a special termination feature that maintains
data integrity and validity. If the transmitter is disabled while a data or sync
character is being sent, that character is sent as usual, but is followed by a
marking line rather than CRC or sync characters. When the transmitter is
disabled, a character in the buffer remains in the buffer. If the transmitter is
disabled while CRC is being sent, the 16-bit transmission is completed, but
sync is sent instead of CRC.
A programmed break is effective as soon as it is written to the control
register; therefore, characters in the transmit buffer and shift register are lost.
In all modes, characters are sent with the least-significant bits first. This
requires right justification of transmitted data if the word length is less than
eight bits. If the word length is five bits or less, the special technique
described in the Write Register 5 discussion (Z80 SIO Programming
section) must be used for the data format. The states of any unused bits in a
data character are irrelevant except when in the Five Bits Or Less mode.
If the External/Status Interrupt Enable bit is set, transmitter conditions such
as “starting to send CRC characters,” “starting to send sync characters,” and
CTS changing state cause interrupts that have a unique vector if Status
Affects Vector is set. This interrupt mode may be used during block transfers.
Serial Input/Output