Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 274

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

254
Table 7. Bisync Receive Mode (Continued)
UM008101-0601
Function
Data Transfer And
Status Monitoring
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Typical Program Steps
When Interrupt on first character
occurs, the CPU performs the
following:
• Transfers data byte to CPU
• Detects and sets appropriate flags for
control characters (in CPU)
• Includes/Excludes data byte in CRC
checker
• Updates pointers and other
parameters
• Enables Wait/Ready for DMA
operation
• Enables DMA controller
• Returns from Interrupt
When Wait/Ready becomes active, the
DMA controller performs the
following:
• Transfers Data Byte to memory
• Interrupts CPU if a special character
is captured by the DMA controller
• Interrupts the CPU if the last
character of the message is detected
For Message Termination, the CPU
performs the following:
• Transfers RR1 to the CPU
• Sets Ack/Nak Reply Flag based on
CRC result
• Updates pointers and parameters
• Returns from Interrupt
Comments
During the hunt mode, the SIO detects
two contiguous characters to establish
synchronization. The CPU establishes
the DMA Mode and all subsequent data
characters are transferred by the DMA
controller. The controller is also
programmed to capture special
characters (by examining only the bits
that specify ASCII or EBCDIC control
characters) and interrupt the CPU upon
detection. In response, the CPU
examines the status or control characters
and takes appropriate action, such as
CRC enable update.
The SIO interrupts the CPU for error
condition, and the error routine aborts
the present message, clears the error
condition, and repeats the operation.
Serial Input/Output