Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 63

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
 
read and write cycles can be programmed for different timing requirements.
If multiple channels are needed, multiple Z80 DMAs can be easily inte-
grated. The interrupt structure is fast and versatile. Interrupt signals and
vectors can be generated under several conditions. Finally, the Z80 DMA
passes data through itself and can therefore compare bytes against a bit-
maskable match byte. An overview of Z80 DMA features are listed below
and each point is described more thoroughly in this and other chapters.
Throughout the remainder of this manual the Z80 DMA is referred to as the
DMA. This DMA is available as either the 2.4 MHz Z80 DMA or the 4 MHz
Z80A DMA. Both parts have the same features and differ only in speed.
Programming
The Z80 DMA has 21 writeable 8-bit control registers and 7 readable 8-bit
status registers available to the CPU. Control bytes can be written to the
DMA or status bytes can be read from the DMA whenever the DMA is not
controlling the bus.
Control bytes writeable to the DMA include those that effect immediate
command actions such as enable, disable, reset, load starting addresses,
continue transferring or searching, clear byte and address counters, clear
status bits, and more. In addition, many mode-setting control bytes can be
written, including the class and mode of operation, port configuration,
starting addresses, block length, address-counting rule, match and match-
mask bytes, interrupt conditions, interrupt vector, end-of-block rule, Ready-
line and Wait-line rules, and others.
Readable status registers include a general status byte that reflects Ready-
line, end-of-block, byte-match, and interrupt conditions, as well as registers
for the current byte count and port addresses. There is a full chapter on
programming on page 90 that explains these functions in detail, and most of
them are described in general terms on the pages that follow.
UM008101-0601
Direct Memory Access