Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 62

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Overview
•
•
•
•
•
The Z80 DMA performs data transfers and searches in a wide variety of
8-bit CPU environments. This DMA is unique among DMACs because it
takes full control of the system address, data, and control buses, and is
therefore a special-purpose processor when enabled by the CPU to
function in this unique way. The DMA also provides complete interfacing
to the system bus. For example, in a Z80 CPU environment, the Z80
DMA generates the same signal levels and timings, including tristate
control, which the Z80 CPU generates to accomplish a transfer. It
normally does this without external TTL packages, which other DMAs
may require.
For this reason, and because of its extensive programmability for operating
on data and dataflow, the Z80 DMA can be called a special-purpose transfer
processor. It unburdens not only the CPU but also the system designer.
The Z80 DMA is also unique in other respects. First, it generates two port
addresses instead of one. Because both addresses can be either variable or
fixed, the memory-to-memory or I/O-to-I/O transfers can be done with a
single channel, whereas other DMACs may require more than one
channel or may not do such transfers at all.
The capability of the Z80 DMA’s channel surpasses the capability of any
other available monolithic DMAC channel to service either fast or slow
devices. In addition to having a Wait line for extending cycles, the basic
Programmable Force Ready Condition
Programmable Active State for Ready Line
Programmable DMA Enable
Complete System Bus Mastering
No External Logic Needed for Sequential Transfers in Z80
Environments
Direct Memory Access