Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 187

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Interrupt on RDY (interrupt before requesting the bus) does not directly
affect the BUSREQ line. Instead, the interrupt service routine may handle
this by issuing the following commands to WR6:
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Pulse Generation
When the pulse generation option is selected, the INT line is driven Low
every 256 bytes after the offset value. The line goes Low during the DMA
cycle in which the pulse-control byte matches the lower byte of the byte
counter, and it remains Low for one complete transfer cycle. A transfer
cycle is defined as either a read cycle (search-only or simultaneous transfer
operations) or a read plus a write cycle, where read and write cycles can be
independently programmed for length through the variable-cycle option.
Enable after Return From Interrupt (RETI) Command — B7H
An RETI instruction that resets the Interrupt Under Service (IUS)
latch in the Z80 DMA — EDH, 4DH.
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Direct Memory Access
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