Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 76

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Byte Matching (Searching)
Variable addresses can either increment or decrement automatically from
the programmed starting address. Fixed addresses are useful for I/O devices
and the DMAs capability to generate fixed addresses eliminates the need
for transfer/search enabling wires to the I/O device (although Chip Enable
hardwiring is still required, as it is with all peripheral circuits).
Two readable address counters keep the current address of each port. These
counters are distinct from the starting address registers for each port, that is,
the counters are buffered by the registers. Therefore, new starting addresses
can be written to the DMA whenever the DMA is not holding the bus, for
example, between byte transfers in Byte mode. New starting addresses for a
new block of data can be loaded into the DMA before the transfer of the
current block is finished. Loading new starting addresses does not disturb
the contents of the associated port address counters.
DMA address generation capabilities can be used in the following ways:
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Searches for byte matches can be performed either as a sole function or
simultaneously with transfers. When a byte match is found, a status bit in
the readable status register is set and the DMA can be programmed to do
one of the following:
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Start at a base address and count up or down.
Automatically step back to the beginning at the completion of an
address sequence.
Load new starting addresses or reload previous ones for the next
sequence.
Stop (release the bus) immediately upon byte match.
Stop and interrupt the CPU immediately upon byte match.
Interrupt the CPU when the DMA stops at the end of a block.
Direct Memory Access