Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 56

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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7 U G T / C P W C N
Transfer Methods
Figure 16 compares conventional CPU instructions and the Z80 and Z8000
CPU block transfer instructions as well as two different methods of DMA
transfer. This figure compares the read and write cycles to the transfer of a
single byte of data.
Figure 16a illustrates conventional CPU I/O instruction activity. The
number of read and write cycles is approximate, some CPUs require more
cycles. The CPU instruction executes all the steps illustrated in Figure 15,
plus additional housekeeping tasks.
Figure 16b illustrates Z80 and Z8000 CPU block transfer instructions.
These instructions are approximate and require more activity than one read
cycle and one write cycle after initiation, especially with the Z80 CPU. A
single block transfer instruction is capable of transferring up to 64 Kbytes
of data.
Figure 16c illustrates sequential or flow-through DMA transfer where a
byte is read from the source port to the DMA and then written to the desti-
nation port. This method can be implemented on the Z80 DMA with no
external logic in a Z80 CPU environment. Sequential transfer provides
speeds that match or exceed the capability of most serial communication
processors and many other I/O or memory devices.
Figure 16d illustrates simultaneous or flyby DMA transfer where a byte is
both read and written in the same machine cycle. Read and Write control
lines are both active. Source and destination are determined by signals that
specify either a memory-read with an I/O-write or an I/O read/memory-
write. This is the fastest transfer method, but the external logic required
makes timing interfaces to memory and I/O somewhat more complicated.
Another method used for some DMACs is called a Transparent or Cycle-
stealing transfer. This technique is similar to the instruction in Figure 16c,
except that control of the bus causes the DMA data transfers to be inter-
leaved with CPU cycles (dynamic memory is not refreshed). This method
Direct Memory Access