Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 154

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Figure 53.
Bus Buffering
Microcomputer systems using DMA often include large memories, many
peripheral devices, or occupy several circuit cards. In these cases, the
system buses and control signals require buffering to increase drive capa-
bility and noise margin and to decrease delay times.
The need for buffering within a single circuit card can be estimated by
comparing drive capabilities of bus master devices (CPU and DMA) to
loadings presented by all inputs and outputs connected to the buses. Both
static (DC current) and dynamic (capacitive drive) requirements must be
considered. When driving a motherboard or other cards, buffering is a prac-
tical necessity.
If the bus master devices (CPU and DMAs) are on the same card, they can
share buffers for address, data, and control buses to other cards. Otherwise,
each card’s bus interfaces require buffering.
Address lines are unidirectional and can be buffered by many common
devices such as 74LS244 and 74LS367 (non-inverting tristate buffer/
drivers) or 74LS240 and 74LS366 (inverting tristate buffer/drivers). The
tristate enable inputs on buffers such as these allow the bus to be isolated
BUSACK
MWR
CLK
Delaying the Leading Edge of MWR
CLK
+5V
D
74LS74
PRE
1/2
Q
DMWR
Direct Memory Access