Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 248

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

228
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
routine in the memory. To service operations in both channels and to elimi-
nate the necessity of writing a status analysis routine, the Z80 SIO can
modify the interrupt vector in RR2 so that it points directly to one of eight
interrupt service routines. This is done under program control by setting a
program bit (WR1, D2) in Channel B called “Status Affects Vector.” when
this bit is set, the interrupt vector in WR2 is modified according to the
assigned priority of the various interrupting conditions. The table in
Register 1” on page 279
Transmit interrupts, Receive interrupts, and External/ Status interrupts are
the main sources of interrupts
enabled under program control with Channel A having a higher priority
than Channel B, and with Receiver, Transmit, and External/Status inter-
rupts prioritized in that order within each channel. When the Transmit
interrupt is enabled, the CPU is interrupted by the transmit buffer
becoming empty. This implies that the transmitter had a data character
written into it so it can become empty. When enabled, the receiver can
interrupt the CPU in one of three ways:
•
•
•
Interrupt On First Character is typically used with the Block Transfer mode.
Interrupt On All Receive Characters has the option of modifying the inter-
rupt vector in the event of a parity error. The Special Receive Condition
interrupt can occur on a character or message basis, for example, End-of-
Frame interrupt in SDLC. The Special Receive condition can cause an
interrupt only if the Interrupt On First Receive Character or Interrupt On
All Receive Characters mode is selected. In Interrupt On First Receive
Character, an interrupt can occur from Special Receive conditions (except
Parity Error) after the first receive character interrupt, for example, Receive
Overrun interrupt.
The main function of the External/Status interrupt is to monitor the signal
transitions of the CTS, DCD, and SYNC pins; however, an External/Status
Interrupt on first receive character
Interrupt on all receive characters
Interrupt on a Special Receive condition
lists the modification details.
(Figure
110). Each interrupt source is
Serial Input/Output
“Write