Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 51

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Direct Memory Access
DMA OVERVIEW
UM008101-0601
CPU Data Transfers
Direct Memory Access (DMA) and DMA Controllers are dedicated to
controlling high-speed block transfers of data independently of the CPU.
DMA data transfers are usually between memory and I/O, or vice versa.
A DMA controller (DMAC) also performs some transfers that have tradi-
tionally been done by the CPU. For example, the Z80 DMA can perform
memory-to-memory, memory-to-I/O, and I/O-to-memory transfers, as
well as search for particular patterns of bits in a byte either simulta-
neously with or independently of transfers.
The advantages of DMA transfers are:
•
•
In systems without DMA, data transfers must pass through the CPU and be
implemented in software. Data transfers through the CPU include
executing an instruction sequence for input and output, and tracking each
byte of data in the block to be transferred.
Figure 15 illustrates the minimum sequence of instructions that must be
fetched from memory and executed by conventional CPUs to transfer a
block of data one byte at a time. Most CPUs require many more instructions.
CPU transfers are relatively slow and tie up the CPU. In addition response
time (startup time for the first byte) is also usually slow because the I/O
device typically uses interrupts to signal its readiness, and the CPU interrupt
service routine causes a significant time lag in transferring the first byte.
Transfers bypass the CPU
Transfers are fast
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N