Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 72

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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attains the bus, the transfers are made at maximum speed. If the transfers
are long, however, this mode can interfere with other CPU activities, which
come to a halt for the entire duration of DMA transfers.
In the Continuous mode (Figure 23), the DMA requests the bus in the same
manner as other modes and repetitively transfers bytes in the same manner
as Burst mode. However, unlike the Burst mode the bus is retained by the
DMA whenever an inactive Ready signal is encountered prior to a stop on
end-of-block or byte match. The DMA simply idles, while holding onto the
bus, until Ready becomes active again. Then it completes the transfer
sequence. This is the fastest of the three modes because it eliminates the
necessity of releasing the bus and requesting it again between complete
block transfers. In this mode, however, the system bus is continuously
preempted by the DMA. This mode is usually used only when very fast
transfers are required and when the impact on CPU activities can be
tolerated. This might be the case, for instance, when an operating system is
being loaded to memory from disk.
Due to the DMA’s high-speed buffered method of reading data, operations
on one byte are not completed until the next byte is read in. This means that
total transfer or search block lengths must be two or more bytes, even in the
Byte mode, and that block lengths programmed into the DMA must be one
less than the desired block length. This characteristic is described in detail
in Internal Structure under the section entitled, “Address and Byte
Counting” on page 75.”
Direct Memory Access