Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 186
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
- Current page: 186 of 330
- Download datasheet (3Mb)
UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
4-Cycle Memory
(4-Cycle I/O
(3-Cycle and
Operations)
Operations)
CE/WAIT
CE/WAIT
CLK
and any functions created from it by external logic in simultaneous transfer
operations (such as IOWR and IORD), remain active during an inactive
RDY line before stopping on end-of-block or byte match.
Interrupts
Timings for interrupt acknowledge and return from interrupt are the same
as timings for these in other Z80 peripherals. Figure 74 illustrates this
timing. The interrupt signal INT is sampled by the CPU on the rising edge
of the final clock cycle of any instruction. The signal is not accepted if the
internal CPU software-controlled interrupt-enable flip-flop is not set or if
the BUSREQ signal is active. When the INT signal is accepted, a special
M1 cycle is generated.
Figure 74.
During this special M1 cycle, the IORQ signal becomes simultaneously
active (instead of the normal MREQ), indicating that the interrupting
device can place its 8-bit vector on the data bus. Two wait states are auto-
matically added to this cycle. These states are added so that a ripple-priority
interrupt scheme can be easily implemented. The two wait states allow time
for the ripple signals to stabilize and identify what I/O device must respond.
Refer to the Z80 CPU User’s Manual for more details.
T
1
WAIT Line Sampling in Variable-Cycle Timing
T
2
T
3
T
4
Direct Memory Access
Related parts for Z0847006PSG
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Customer Procurement Spec(CPS)
Manufacturer:
ZILOG [Zilog, Inc.]
Datasheet:
Part Number:
Description:
Communication Controllers, ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP)
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
KIT DEV FOR Z8 ENCORE 16K TO 64K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
KIT DEV Z8 ENCORE XP 28-PIN
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
DEV KIT FOR Z8 ENCORE 8K/4K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
KIT DEV Z8 ENCORE XP 28-PIN
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
DEV KIT FOR Z8 ENCORE 4K TO 8K
Manufacturer:
Zilog
Datasheet:
Part Number:
Description:
CMOS Z8 microcontroller. ROM 16 Kbytes, RAM 256 bytes, speed 16 MHz, 32 lines I/O, 3.0V to 5.5V
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Low-cost microcontroller. 512 bytes ROM, 61 bytes RAM, 8 MHz
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
Z8 4K OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
CMOS SUPER8 ROMLESS MCU
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
SL1866 CMOSZ8 OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
SL1866 CMOSZ8 OTP Microcontroller
Manufacturer:
Zilog, Inc.
Datasheet:
Part Number:
Description:
OTP (KB) = 1, RAM = 125, Speed = 12, I/O = 14, 8-bit Timers = 2, Comm Interfaces Other Features = Por, LV Protect, Voltage = 4.5-5.5V
Manufacturer:
Zilog, Inc.
Datasheet: