Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 207

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROGRAMMING THE PIO
UM008101-0601
Reset
Figure 6.
The Z80 PIO automatically enters a reset state when power is applied. The
reset state performs the following functions:
1. Both port mask registers are reset to inhibit all port data bits.
2. Port data bus lines are set to a high-impedance state and the Ready
3. The vector address registers are not reset.
4. Both port interrupt enable flip-flops are reset.
5. Both port output registers are reset.
ARDY
ASTB
BSTB
GND
C/D
PA
PA
PA
PA
PA
PA
PA
PA
B/A
CE
D
D
D
D
D
handshake signals are inactive (Low). Mode 1 is automatically selected.
2
7
6
7
6
5
4
3
2
1
0
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Z80
PIO
40-Pin DIP Pin Assignments
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D
D
D
M1
IORQ
RD
PB
PB
PB
PB
PB
PB
PB
PB
+5V
CLK
IEI
INT
IEO
BRDY
3
4
5
7
6
5
4
3
2
1
0
<   % 2 7 2 G T K R J G T C N U
Parallel Input/Output
7 U G T / C P W C N