Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 123

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Write Register 6 Group
Figure 45.
The base register byte for this group has bits 7, 1, and 0 set to one, which
Figure 46 depicts. The remaining bits specify 16 commands that are
commonly used after DMA initialization (for example, within CPU
interrupt service routines), and to point to a read mask for the read registers.
Each of these commands, except the ENABLE DMA command, disables
the DMA. Therefore, the ENABLE DMA command must be the last
command written before DMA bus requests can begin.
Reset (C3)
This command is used at power-up and when aborting a program sequence
to do the following:
•
•
•
•
•
D7 D6 D5 D4 D3 D2 D1 D0
1
0
Disable interrupt and bus-request logic
Reset interrupt latches
Unforce a FORCE READY condition
Reset the Auto Repeat function (see WR5)
Reset the Wait function (See WR5)
0 = Stop on End-of-Block
1 = Auto Restart on End-of-Block
0 = CE Only
1 = CE/WAIT Only
0 = Ready Active Low
1 = Ready Active High
Write Register 5 Group
0
1
0
Base Register Byte
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N