Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 244

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

224
UM008101-0601
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7 U G T / C P W C N
entered in the 3-bit buffer if the data has a character length of seven or eight
bits, or is entered in the 8-bit receive shift register if the data has a length of
five or six bits.
In the Synchronous mode, the data path is determined by the phase of the
receive process currently in operation. A Synchronous Receive operation
begins with the receiver in the Hunt phase, during which the receiver
searches the incoming data stream for a bit pattern that matches the prepro-
grammed sync characters for flags in the SDLC mode. If the device is
programmed for Monosync Hunt, a match is made with a single sync char-
acter stored in WR7. In Bisync Hunt, a match is made with dual sync char-
acters stored in WR6 and WR7.
In either case, the incoming data passes through the receive sync register,
and is compared against the programmed sync character in WR6 or WR7.
In the Monosync mode, a match between the sync character programmed to
WR7 and the character assembled in the receive sync register establishes
synchronization.
In the Bisync mode, however, incoming data is shifted to the receive shift
register while the next eight bits of the message are assembled in the
receive sync register. The match between the assembled character in the
receive sync registers with the programmed sync character in WR6 and
WR7 establishes synchronization. When synchronization is established,
incoming data bypasses the receive sync register and directly enters the
3-bit buffer.
In the SDLC mode, incoming data first passes through the receive sync
register, which continuously monitors the receive data stream and
performs zero deletion when indicated. Upon receiving five contiguous
1s, the sixth bit is inspected. If the sixth bit is a 0, it is deleted from the
data stream. If the sixth bit is a 1, the seventh bit is inspected. If the
seventh bit is a 0, a Flag sequence has been received; if it is a 1, an Abort
sequence has been received.
The reformatted data enters the 3-bit buffer and is transferred to the receive
shift register. The SDLC receive operation also begins in the Hunt phase,
Serial Input/Output