Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 232

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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UM008101-0601
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general-purpose inputs. Both inputs are Schmitt-trigger buffered to
accommodate slow-risetime inputs. The Z80 SIO detects pulses on these
inputs and interrupts the CPU on both logic level transitions. The
Schmitt-trigger inputs do not guarantee a specified noise-level margin.
DCDA, DCDB Data Carrier Detect (inputs, active Low). These signals
are similar to the CTS inputs, except they can be used as receiver enables.
RxDA, RxDB Receive Data (inputs, active High).
TxDA, TxDB Transmit Data (outputs, active High).
RxCA, RxCB* Receiver Clocks (inputs). See the following section on
bonding options. The Receive Clocks may be 1, 16, 32, or 64 times the
data rate in asynchronous modes. Receive data is sampled on the rising
edge of RxC.
TxCA, TxCB* Transmitter Clocks (inputs). See section on bonding
options. In asynchronous modes, the Transmitter clocks may be 1, 16, 32,
or 64 times the data rate. The multiplier for the transmitter and the receiver
must be the same. Both the TxC and RxC inputs are Schmitt-trigger buff-
ered for relaxed rise- and fall-time requirements (no noise margin is speci-
fied). TxD Changes on the falling edge of TxC.
These clocks may be directly driven by the Z80 CTC (Counter Timer
Circuit) for fully programmable baud rate generation.
RTSA, RTSB Request To Send (outputs, active Low). When the /RTS bit is
set, the RTS output goes Low. When the RTS bit is reset in the Asynchro-
nous mode, the output goes High after the transmitter is empty. In Synchro-
nous modes, the RTS pin strictly follows the state of the RTS bit. Both pins
can be used as general-purpose outputs.
DTRA, DTRB Data Terminal, Ready (outputs, active Low). See note on
bonding options. These outputs follow the state programmed into the DTR
bit. They can also be programmed as general-purpose outputs.
SYNCA, SYNCB Synchronization (inputs/outputs, active Low). These
pins can act either as inputs or outputs. In the Asynchronous Receive mode,
Serial Input/Output