Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 46

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Interrupt Acknowledge Cycle
The CTC’s interrupt control logic ensures that it acts in accordance with
Z80 system interrupt protocol for nested priority interrupt and proper return
from interrupt. The priority of any system device is determined by its
physical location in a daisy-chain configuration. Two signal lines (IEI and
IEO) are provided in the CTC to form the system daisy chain. The device
closest to the CPU has the highest priority. Interrupt priority is
predetermined by channel number, with Channel 0 having highest priority.
According to Z80 system interrupt protocol, low priority devices or
channels may not interrupt higher priority devices or channels that have not
had their interrupt service routines completed. High priority devices or
channels may interrupt the servicing of lower priority devices or channels.
(For further details, see “CTC Architecture” on page 2.)
“Return from Interrupt Cycle” on page 29 and “Daisy-Chain Interrupt
Servicing” on page 30 describe the nominal timing relationships of the
relevant CTC pins for the Interrupt Acknowledge cycle and the Return
from Interrupt cycle. “Daisy-Chain Interrupt Servicing” on page 30
discusses a typical example of daisy-chain interrupt servicing.
Figure 12 illustrates the timing associated with the Interrupt Acknowledge
cycle. After an interrupt is requested by the CTC, the CPU sends out an
interrupt acknowledge (M1 and IORQ). To insure that the daisy-chain
enable lines stabilize, channels are inhibited from changing their interrupt
request status when M1 is active. M1 is active two clock cycles earlier than
IORQ and RD is false to distinguish the cycle from an instruction fetch.
During this time, the interrupt logic of the CTC determines the highest
priority channel requesting an interrupt. If the CTC Interrupt Enable input
(IEI) is active, the highest priority interrupting channel within the CTC
places its interrupt vector onto the data bus when IORQ goes active. Two
Wait States (TW*) are automatically inserted at this time to allow the daisy-
chain to stabilize. Additional Wait States may be added.
Counter/Timer Channels