Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 251

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
231
registers by the system program. WR4 parameters must be issued before
WR1, WR3, and WR5 parameters or commands.
If the data is transmitted over a modem or RS232C interface, the
REQUEST TO SEND (RTS) and DATA TERMINAL READY (DTR)
outputs must be set along with the Transmit Enable bit. Transmission
cannot begin until the Transmit Enable bit is set.
The Auto Enables feature allows the programmer to send the first data
character of the message to the Z80 SIO without waiting for CTS. If the
Auto Enables bit is set, the Z80 SIO waits for the CTS pin to go Low
before it begins data transmission. CTS, DCD, and SYNC are general-
purpose I/O lines that may be used for functions other than their labeled
purposes. If CTS is used for another purpose, the Auto Enables Bit must
be programmed to 0.
Figure 111 illustrates asynchronous message formats;
Table 3
describes
WR3, WR4, and WR5 with bits set to indicate the applicable modes,
parameters and commands in asynchronous modes. WR2 (Channel B
only) stores the interrupt vector; WR1 defines the interrupt modes and
data transfer modes. WR6 and WR7 are not used in asynchronous modes.
Table 4 describes the typical program steps that implement a full-duplex
receive/transmit operation in either channel.
Asynchronous Format
Marking Line
Start
D0
D1
DN
Parity
Stop
Marking Line
All Transactions Occur
N = 5, 6, 7, or 8
1, 1 1/2, or 2 Bits
on a Falling Edge of TxC
May be present or not
Even or Odd
Message Flow
Figure 111. Asynchronous Message Format
UM008101-0601
Serial Input/Output