Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 273

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7. Bisync Receive Mode (Continued)
UM008101-0601
Function
Idle Mode
WR0
WR1
WR0
WR3
Typical Program Steps
Pointer 1, Reset External/Status
Interrupt
Status Affects Vector, External
Interrupt Enable, Receive Interrupt on
first character only
Pointer 3, Enable Interrupt on next
Receive character
Receive Enable, sync character load
inhibit, enter Hunt Mode Auto Enable,
receive word length
Execute Halt Instruction or some other
program
Comments
In this interrupt mode, only the first
non-sync data character is transferred to
the CPU. All subsequent data is
transferred on a DMA basis; however,
special receive condition interrupts
interrupt the CPU. status affects vector
used in Channel B only.
Resetting this Interrupt Mode provides
simple program loopback entry for the
next transaction.
WR3 is reissued to enable receiver;
receive CRC enable must be set after
receiving SOH or STX character.
Receive mode is fully initialized and the
system is waiting for interrupt on first
character.
Z80 CPU Peripherals
Serial Input/Output
User Manual
253