Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 142

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
processed until the bus is released). Second, to enable the DMA, the
ENABLE AFTER RETI
an Interrupt on Ready. The typical purpose of interrupting when the Ready
line comes active is to allow the CPU time to determine where a transfer
should go, which it does in the service routine. This often occurs in systems
with dynamic memory allocation and it improves the efficiency with which
memory can be allocated. For example, the CPU might write and load new
starting addresses for a memory destination to the DMA in the service
routine. Only at the end of the service routine is the DMA enabled to
request the bus. The
the
Ready first occurred.
For non-Z80 CPU environments, the
INTERRUPTS
available. They can simulate the Z80 CPU’s interrupt-acknowledge cycle
and return-from-interrupt instruction, both of which the DMA needs to
perform and return from interrupts.
Byte Matching (Searches)
In stopping, or stopping and interrupting on match (WR3, WR4), to
perform additional operations with the DMA, the following sequence of
commands are written:
1.
2.
3.
Another command (with the exception of
REINITIALIZE STATUS BYTE
the contents of various counters when stopping on byte match.
ENABLE DMA
LOAD
REINITIALIZE STATUS BYTE.
ENABLE DMA.
or
CONTINUE.
, and
command, resets a latch that is set when the Interrupt on
RESET AND DISABLE INTERRUPTS
ENABLE AFTER RETI
command must be used in the service routine after
command. Table 11 on page 76 describes
DISABLE INTERRUPTS
ENABLE DMA
command, which must precede
Direct Memory Access
) must precede the
commands are
,
ENABLE