Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 99

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
 
status bit is not set as it would be without the Auto Restart. Therefore, the
interrupt vector cannot indicate the specific interrupt cause, for example,
Status Affects Vector is not effective.
The Z80 CPU acknowledges the interrupt by pulling its M1 and IORQ lines
low for one machine cycle (see the “Timing” chapter). This causes the
DMA to put its 8-bit interrupt vector on the data bus, thereby identifying
itself and optionally identifying the origin of the interrupt. The CPU uses
the vector to access an interrupt service routine, which is then executed.
The interrupt service routine typically reenables the DMA to request the
bus and cause interrupts again.
For CPUs that have no interrupt acknowledge or a noncompatible one,
DMA control bytes can be written (usually in the interrupt service routine)
to simulate the same functions.
UM008101-0601
Direct Memory Access