Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 327

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
307
T
T
T
T
T
T
1
2
W
W
3
4
Φ
M1
IORQ
RD
IEI
Data
Vector
Figure 130. Interrupt Acknowledge Cycle Timing
Return From Interrupt Cycle
Normally, the Z80 CPU issues a RETI, RETurn from Interrupt, instruction
at the end of an interrupt service routine. The RETI is a 2-byte Op Code,
ED-4D, which resets the interrupt-underservice latch that terminates the
interrupt just processed. This is accomplished by manipulating the daisy-
chain in the following way.
The normal daisy-chain operation can detect a pending interrupt; however,
it cannot distinguish between an interrupt under service and a pending
unacknowledged interrupt of a higher priority. Whenever ED is decoded,
the daisy-chain is modified by forcing High the IEO of any interrupt not yet
acknowledged.
Thus the daisy-chain identifies the device presently under service as the
only one with an IEI High and an IEO Low. If the next Op Code byte is 4D,
the interrupt-underservice latch is reset. See Figure 131.
UM008101-0601
Serial Input/Output