Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 297

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Table 14. Reset Commands
The Reset Transmit CRC Generator command normally initializes the CRC
generator to 0s. If the SDLC mode is selected, this command initializes the
CRC generator to 1s. The Receive CRC checker is also initialized to 1s for
the SDLC mode.
Write Register 1
WR1
Wait/Ready modes.
Table 15. Write Register 1
External/Status Interrupt Enable (D0)
The External/Status Interrupt Enable allows interrupts to occur as a result of
transitions on the DCD, CTS, or SYNC inputs, as a result of a Break/Abort
D7
Wait/Ready
Enable
D3
Receive Interrupt
Mode 0
CRC Reset
Code 1
0
0
1
1
(Figure
115) contains the control bits for the various interrupt and
CRC Reset
Code 0
0
1
0
1
D6
Wait or Ready
Function
D2
Status Affects
Vector
Result
Null Code (no affect)
Reset Receive CRC Checker
Reset Transmit CRC Generator
Reset Tx Underrun/End of Message latch
D5
Wait/Ready on
Receive Transmit
D1
Transmit Interrupt
Enable
Z80 CPU Peripherals
Serial Input/Output
D4
Receive Interrupt
Mode 1
D0
External Interrupts
Enable
User Manual
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