Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 271

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Note:
before the next character is transferred, CRC is calculated on the transferred
character. If CRC is disabled before the time of the next transfer, calcula-
tion proceeds on the word in progress, but the word just transferred to the
buffer is not included. When these requirements are satisfied, the 3-byte
receive data buffer is, in effect, unusable in Bisync operation. CRC may be
enabled and disabled as many times as necessary for a given calculation.
In the Monosync, Bisync, and External Sync modes, the CRC/Framing Error
bit (RR1, D6) contains the comparison result of the CRC checker 16-bit
times (eight bits delay and eight shifts for CRC) after the character has been
transferred from the receive shift register to the buffer. The result should be
zero, indicating an error-free transmission.
The comparison is made with each transfer and is valid only as long as the
character remains in the receive FIFO.
Following is an example of the CRC checking operation when four charac-
ters (A, B, C, and D) are received in that order.
•
•
If CRC is disabled before C is in the buffer, CRC is not calculated on B.
•
After C is loaded, the CRC/Framing Error bit shows the result of the
comparison through character A.
•
After D is in the buffer, the CRC Error bit shows the result of the comparison
through character B whether or not B was included in the CRC calculations.
Due to the serial nature of CRC calculation, the Receive Clock (RxC)
must cycle 16 times (8-bit delay plus 8-bit CRC shift) after the second
Character A loaded to buffer
Character B loaded to buffer
Character C loaded to buffer
Character D loaded to buffer
The result is valid only at the end of CRC calculation. If the result
is examined before this time, it usually indicates an error.
Z80 CPU Peripherals
Serial Input/Output
User Manual
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