Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 22
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number:
Z0847006PSG
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UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
In Channel Control Register and Logic
The Channel Control register (8-bit) and Logic is written to by the CPU to
select the modes and parameters of the channel. Within the CTC device,
four such registers correspond to the four Counter/Timer channels. The
register to be written to is determined by the encoding of two channel select
input pins: CS0 and CS1, which are usually attached to A0 and A1 of the
CPU address bus. The channel values are described in Table 1.
Table 1. Channel Values
In the control word, which is written to program each Channel Control
register, bit 0 is always set; the other seven bits are programmed to select
alternatives on the channel’s operating modes and parameters. These values
are described in Table 2. For a more complete discussion, see “CTC
Operating Modes” on page 16 and “CTC Programming” on page 18).
Figure 2.
Internal Bus
CLK/TRG
CLK
Channel 0
Channel 1
Channel 2
Channel 3
Channel Block Diagram
Prescaler
CS0
0
0
1
1
Constant
Register
Channel
Control
Counter
Logic
Time
Down
8-Bit
CS1
0
1
0
1
ZC/TO
Counter/Timer Channels
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