Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 119

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Starting Address (Port B)
The starting address for Port B in the next two bytes may be specified by
setting bits 2 and 3 of the base register to 1. This is only needed if Port B is
used, and then it specifies the first address at which a byte is read from or
written to, depending on whether the port is declared a source or destination
in WR0. If Port B is to be a fixed-address destination, see “Fixed-Address
Destination Ports” on page 121.
Interrupts
Bit 4 of the base register byte can point to the interrupt control byte, and
bits 4 and 3 of the interrupt control byte can point to the interrupt vector and
pulse control bytes, respectively. The interrupt control byte also specifies
one or more of the following three interrupt conditions:
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•
•
Setting any of these bits to 1 enables the interrupt condition but not the
interrupt circuitry itself, which is enabled either through the ENABLE
INTERRUPTS command in WR6 or through bit 5 in WR3. Interrupts do
not occur on these conditions if their associated bits are 0 in the interrupt
control byte. Table 13 and Table 15 in the previous chapter apply to these
interrupt conditions because the DMA releases the bus (stops) before inter-
rupting the CPU.
Interrupt on match (bit 0), if stop on match or stop on end-of-block is
also programmed
Interrupt at end-of-block (bit 1), if stop on end-of-block is also
programmed
Interrupt on Ready (bit 6), for example, interrupt before requesting
the bus when the Ready line becomes active
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N