Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 277

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
257
“Synchronous Operation” on page 238
section for more details on the
interrupt modes.
After reset, or when the transmitter is not enabled, the Transmit Data output
is held marking. Break may be programmed to generate a spacing line.
With the transmitter fully initialized and enabled, continuous flags are
transmitted on the Transmit Data output.
An abort sequence may be sent by issuing the Send Abort command WR0
CMD1). The Send Abort command causes at least 8, but less than 14, 1s to
be sent before the line reverts to continuous flags. It is possible that the
Abort sequence (eight 1s) could follow up to five continuous 1 bits
(allowed by the zero insertion logic) and thus cause up to thirteen 1s to be
sent. Any data being transmitted and any data in the transmit buffer is lost
when an abort is issued.
When required, an extra 0 is automatically inserted when five contiguous
1s occur in the data stream. Automatic insertion does not apply to flags or
aborts.
Data Transfer and Status Monitoring
SDLC mode allows several combinations of interrupts and Wait/Ready
functions.
Data Transfer Using Interrupts
If the Transmit Interrupt Enable bit is set, an interrupt is generated when the
buffer becomes empty. The interrupt may be satisfied either by writing
another character to the transmitter or by resetting the Transmit Interrupt
Pending latch with a Reset Transmitter Pending command (WR0, CMD5).
If the interrupt is satisfied with this command and no more is written to the
transmitter, then no more transmitter interrupts occur. The result is a
Transmit Underrun condition. When another character is written and sent,
the transmitter can again become empty and interrupt the CPU. Following
the flags in an SDLC operation, the 8-bit address field, control field and
UM008101-0601
Serial Input/Output