Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 262

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

242
Table 6. Bisync Transmit Mode
UM008101-0601
Function
Initialize WR0
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Register Information loaded
WR0
WR2
WR0
WR3
WR0
WR4
WR0
WR6
WR0
WR7
WR0
WR1
Typical Program Steps
Channel Reset, Reset Transmit CRC
Generator
Pointer 2
Interrupt Vector
Pointer 3
Auto Enables
Pointer 4
Parity Information, Sync Modes
Information, X1Clock Mode
Pointer 6
Sync Character 1
Pointer 7, Reset External/Status Interrupts
Sync Character 2
Pointer 1, Reset External/Status Interrupts
Status Affects Vector, External Interrupt
Enable, Transmit Interrupt Enable or
WAIT/READY Mode Enable
Comments
Reset SIO, Initialize CRC Generator
Channel B only
Transmission begins only after CTS
is detected
Issue transmit parameters
External Interrupt Mode monitors
the status of CTS and DCD input
pins as well as the status of Tx
Underrun/EOM Latch. Transmit
Interrupt Enable interrupts when the
transmit buffer becomes empty; the
WAIT/READY Mode can be used to
transfer data using DMA or CPU
block transfer.
Serial Input/Output