Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 198

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
(2 Bits)
Control
Mask
Reg
Mode Control Reg
Figure 2.
Use the 8-bit mask register and the 8-bit input/output select register only
in the Bit Control mode. In this mode, any of the eight peripheral data or
control bus pins can be programmed to be an input or an output as speci-
fied by the select register. The mask register is used in this mode in
conjunction with a special interrupt feature. This feature allows an inter-
rupt to be generated when any or all of the unmasked pins reach a speci-
fied state (either High or Low).
The 2-bit mask control register specifies the active state desired (High or
Low) and if the interrupt should be generated when all unmasked pins are
active (AND condition) or when any unmasked pin is active (OR condi-
tion). This feature reduces the requirement for CPU status checking of the
peripheral by allowing an interrupt to be automatically generated on
specific peripheral status conditions. For example, in a system with three
alarm conditions, an interrupt may be generated if any one occurs or if all
three occur.
Internal Bus
(2 Bits)
(8 Bits)
Mask
Reg
Port I/O Block Diagram
Requests
Interrupt
Input Data
Input/Output Select Reg
Data Output Reg
Handshake Control Logic
Data Input
(8 Bits)
(8 Bits)
(8 Bits)
(2 Bits)
Output Enable
Ready
Parallel Input/Output
Strobe
8-Bit Peripheral Data
or Control Bus
Handshake
Lines