Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 296

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Command 4 (Enable Interrupt On Next Receive Character). If the Interrupt
On First Receive Character mode is selected, command 4 reactivates the
Enable Interrupt On Next Receive Character mode after receiving each
complete message. This sequence prepares the Z80 SIO for the next message.
Command 5 (Reset Transmitter Interrupt Pending). A transmitter interrupt
occurs when the transmit buffer becomes empty. This interrupt happens
only when the Transmit Interrupt Enable mode is selected. When there are
no more characters to be sent for example, at the end of message, issuing
this command prevents further transmitter interrupts until after the next
character is loaded to the transmit buffer or until CRC is completely sent.
Command 6 (Error Reset). This command resets the error latches. Parity
and Overrun errors are latched in RR1 until they are reset with this
command. Using this method, parity errors occurring in block transfers can
be examined at the end of the block.
Command 7 (Return From Interrupt). This command must be issued in
Channel A and is interpreted by the Z80 SIO in the same way it interprets
an RETI command on the data bus. This command resets the interrupt
under-service latch of the highest priority internal device under service.
This reset allows lower-priority devices to interrupt through the daisy-
chain. This command also allows use of the internal daisy-chain even in
systems with no external daisy-chain or RETI command.
CRC Reset Codes 0 and 1 (D6 and D7). Used together, these bits select one
of the three following reset commands, described in
Table
Serial Input/Output
14: