Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 215
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
Z0847006PSG
Manufacturer:
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UM008101-0601
Data Bus
ARDY
Port A
BRDY
ASTB
BSTB
WR*
INT
Φ
WR
Control Mode (Mode 3)
*
= RD • CE • C/D • IORQ
after this edge has risen. The input portion of Mode 2 operates identically to
Mode 1. Notice that both Port A and Port B must have their interrupts
enabled to achieve an interrupt-driven, bidirectional transfer.
The peripheral must not gate data onto a port data bus while ASTB is
active. Bus contention is avoided when the peripheral uses BSTB to gate
input data onto the bus. The PIO uses the BSTB low level to latch this data.
The data can be disabled from the bus immediately after the strobe rising
edge. This is because the PIO has been designed with a zero hold time
requirement for the data when latching in this mode. This gating structure
can be used by the peripheral.
Figure 9.
The control mode does not utilize the handshake signals, therefore a normal
port write or port read can be executed at any time. When writing, the data
is latched to output registers with the same timing as Mode 0. ARDY is
forced low whenever Port A is operated in Mode 3. BRDY is held Low
whenever Port B is operated in Mode 3 unless Port A is in Mode 2. In the
latter case, the state of BRDY is not affected.
Port A, Mode 2 (Bidirectional) Timing
Data Out
Sample
Data In
< % 2 7 2 G T K R J G T C N U
Parallel Input/Output
7 U G T / C P W C N
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